This invention relates to phase lock loop circuits and particular to phase lock loop circuits used in digital communications.
Digital radios used in the next generation of satellite radio receivers have been specified to sample the demodulated digital data at a sampling frequency of 48 kHz (Kilohertz) plus or minus 100 ppm (parts per million). Each digital radio has no way of knowing what is the exact sampling frequency of the source (i.e. transmitter). In the situation where the receiver sampling frequency is operating at 48 kHz and the transmitter sampling frequency is 48 kHz plus 100 ppm, the receiver, over time, will overflow. A microprocessor connected to a sample buffer in the receiver can detect this overflow condition by the accumulation of samples in the buffer. If the transmitter sampling frequency is 48 kHz minus 100 ppm and the receiver sampling frequency is 48 kHz then an underflow condition will occur. Likewise, a microprocessor connected to a sample buffer in the receiver can detect this underflow condition by the depletion of samples in the buffer. The overflow and underflow conditions are avoided by making changes to the receiver's sampling frequency. However, only course adjustments to the sampling clock can be made resulting in audible distortion in the signal.
An oscillator in the receiver matched to the transmitter oscillator would not offer a practical solution to the above identified problem for a number of reasons. Firstly, all transmitters and receivers would require matched oscillators, an impractical requirement. Secondly, the signal's transmission path could introduce short term variations in the rate, in the receiver this would manifest itself in the same way as a mismatch in the transmitter and receiver rates.
A Phase Lock Loop (PLL) circuit is typically used in the receiver to generate the sample frequency. The PLL includes a voltage controlled oscillator (VCO) that provides the sampling frequency (or an integer multiple of) as an output. The voltage that controls the VCO is provided by comparing a stable reference frequency, Fref, with a feedback signal, Ffb. The action of the PLL causes the voltage to change so that Ffb equals Fref. In direct frequency synthesis Ffb is derived by dividing the VCO output frequency, Fvco, by N. Following the comparison of Fref and Ffb, the control voltage can cause Fvco to increase or decrease based upon the results of the comparison. However, this type of feedback arrangement holds the Fvco frequency to N times the reference frequency and thereby restricting the resolution in the sampling clock. It is possible to have a very large N, so given the necessary resolution in Fvco, however, this places very severe demands on the PLL circuitry.
Indirect frequency synthesis was discussed in the 1993 IEEE paper 0018-9200/93$03.00 in an article entitled Delta-Sigma Modulation in Fractional-N Frequency synthesis by Tom A. D. Riley, Miles Capeland and Tad A. Kwasniewski, and in a two part article in Electronics World (February and March 1996) entitled Fractional-N Synthesis by Cosmo Little. In these articles the authors described delta sigma modulation and fractional-N frequency division techniques to perform indirect digital frequency synthesis based upon the use of a PLL. However, the techniques described had a number of short comings. In the first paper, there are restrictions on the operational range of the PLL. In the second paper, the PLL's jitter performance is less than satisfactory for certain frequency values. Both of these short comings are over come in this invention.